The progressive and continuous miniaturization of electronic circuits makes it possible to obtain circuits that continue to increase in performance while continuing to decrease in size. On the down side, such circuits are increasingly sensitive to their external environment, and in particular to logic upsets due to an influx of energy coming from outside the circuit. A logic upset is a point state change or a transient state, resulting from a voltage spike and/or a current spike at a point in an integrated circuit. By definition, an upset is not predictable or is very unlikely to be predicted.
Logic upsets may have different origins. A logic upset is, for example, induced by the impact of an energetic charged particle at a point in an integrated circuit. Such an upset is known as a single event upset or SEU. This type of upset appears in integrated circuits used for space applications, because of the radiation encountered beyond the atmospheric and magnetospheric layers that protect the earth. This type of upset is also becoming more frequent in integrated circuits for terrestrial applications, especially in the smallest technologies, such as 0.25 micron, 0.18 micron, 0.12 micron and even finer technologies. A logic upset may also be induced by capacitive coupling at discrete points between two layers of the same integrated circuit. Such an upset is in this case often referred to as a “glitch”.
An upset, whatever its origin, is generally manifested by a voltage and/or current spike on a digital or analog signal at a disturbed point in a circuit, formed by the point of impact of the energetic particle in the case of an SEU upset. If the equivalent capacitance of the circuit downstream of the disturbed point is denoted by C, the change in voltage ΔV at the disturbed point in question can be written as ΔV=ΔQ/C, ΔQ being the change in charge resulting from the impact. The change in voltage ΔV generally has a very short duration, for example very much less than the period of a clock signal driving the circuit.
An upset may have relatively serious consequences on the downstream circuit that it disturbs. For example, for a downstream circuit using only logic signals, if the change in voltage ΔV is low enough not to cause a change in state, the disturbance disappears in quite a short time, with no consequence for the downstream circuit. This is especially the case when the equivalent downstream capacitance is high or when the change in charge ΔQ is small. In contrast, if the change in voltage ΔV is higher, and especially if it is high enough to modify the value of a logic signal, then the consequences may be substantial.
In particular, a change in voltage ΔV generated by an upset may disturb the normal operation of a flip-flop multivibrator. Specifically, such a multivibrator generally includes two latch cells, called the master cell and the slave cell, each connected to the output of a transfer port. When an active edge of a clock signal is received by the multivibrator, input data is firstly stored in the master latch cell. The data is transmitted to the second, slave, latch cell and into the output of the multivibrator when an active edge of the clock signal is applied to the second data transfer port. Thus, when the multivibrator receives an active edge of the clock pulse, it reproduces, over the period of the clock signal, on its output, the signal that it receives on its data input.
Now, an upset of substantial amplitude may cause the logic levels present on the input of each latch cell to switch when they are not imposed by a corresponding transfer port. Such switching, that is to say the modification of the content of the latch cells, will, of course, have the consequence of introducing an error into the outputs from the multivibrator.
For the purpose of protecting the multivibrators against upsets and thus preventing any disturbance of the downstream circuit, it has been proposed to produce each latch cell in a redundant manner, that is to say in the form of a set of redundant data storage nodes, so that when an upset causes an alteration in the logic level stored in one of the nodes, the initial information may be restored from the information stored in a complementary node.